Unit 10 : Computer System Architecture

COMPUTER SYSTEM ARCHITECTURE

UGC NET / JRF — Computer Science & Applications

High-Yield Study Notes & PYQ-Pattern Workbook (Unit 10)

Contents

Ch.1 — Digital Logic Circuit & Components

Ch.2 — Data Representation

Ch.3 — Register Transfer & Microoperations

Ch.4 — Basic Computer Organization & Design

Ch.5 — Programming the Basic Computer

Ch.6 — Central Processing Unit

Ch.7 — Pipelining

Ch.8 — Memory Hierarchy & Cache Mapping

One-Shot Revision

Mini Mock Test (Answer Key)

Beginner → Concept → NET-level → JRF-level. Compact by design — exam value over page count.

Chapter 1 — Digital Logic Circuit & Components

1.1 Combinational Circuits — Adders

Circuit	Idea
Half Adder	Adds 2 bits: Sum=A⊕B, Carry=A·B — no carry-IN input
Full Adder	Adds 3 bits (A, B, carry-in Cin): Sum=A⊕B⊕Cin, Carry-out=AB+BCin+ACin
Ripple Carry Adder	Chains n Full Adders to add n-bit numbers — SIMPLE but SLOW (each stage waits for the previous carry)

JRF trapA Half Adder CANNOT be used alone to build a multi-bit adder chain, because it has no carry-IN input — you need a FULL ADDER (which accepts carry-in) for every stage except possibly the very first (least significant bit). This "half adder lacks carry-in, so chains need full adders" distinction is frequently tested.

1.2 Multiplexers & Demultiplexers

IdeaA Multiplexer (MUX) selects ONE of several input lines to route to a SINGLE output, based on select lines (a "digital selector switch"). A Demultiplexer (DEMUX) does the OPPOSITE — takes ONE input and routes it to ONE of several outputs, based on select lines.

An n-to-1 MUX needs log2(n) select lines. A 2^k-to-1 MUX needs k select lines.

JRF-level numericalHow many select lines does a 32-to-1 MUX need? log2(32) = 5 select lines. How many DATA input lines does a MUX with 4 select lines have? 2^4 = 16 inputs. This "select lines ↔ number of inputs via log2/2^k" relationship is a frequently tested MUX numerical.

1.3 Decoders & Encoders

IdeaA Decoder converts n input lines into UP TO 2^n unique output lines (exactly ONE output active for each input combination) — used for memory address decoding. An Encoder does the OPPOSITE — converts 2^n input lines into n output lines (compresses "which single input is active" into a binary code).

TrapA basic Encoder assumes only ONE input is active at a time — if MULTIPLE inputs are active simultaneously, the output becomes ambiguous/incorrect. This is solved by a PRIORITY ENCODER, which resolves conflicts by giving priority to the highest-priority (usually highest-numbered) active input. "Why do we need priority encoders" is a common JRF conceptual question.

1.4 Sequential Circuits — Flip-Flops

Flip-Flop	Behaviour
SR (Set-Reset)	S=1,R=0→Set(Q=1); S=0,R=1→Reset(Q=0); S=R=1 is an INVALID/undefined state
D (Data/Delay)	Output Q simply follows input D at the next clock edge (Q_next = D) — no invalid state
JK	Like SR but J=K=1 causes Q to TOGGLE (flip) instead of being invalid — fixes SR's undefined state
T (Toggle)	T=1→toggles Q every clock edge; T=0→holds current value

JRF trapJK flip-flop is essentially an "improved SR flip-flop" — it resolves SR's problematic S=R=1 invalid state by making J=K=1 cause a TOGGLE instead. This "JK fixes SR's invalid state via toggling" relationship is a very frequently tested flip-flop fact — also remember a T flip-flop can be built from a JK flip-flop by tying J and K together (J=K=T).

1.5 Registers & Counters

Component	Idea
Register	Group of flip-flops storing MULTIPLE bits together (e.g., an 8-bit register = 8 flip-flops)
Shift Register	Register where stored bits can be SHIFTED left/right on each clock pulse (serial in/out, parallel in/out variants)
Asynchronous (Ripple) Counter	Flip-flops triggered in SEQUENCE (each by the previous flip-flop's output) — simple but SLOWER (propagation delay accumulates)
Synchronous Counter	ALL flip-flops triggered by the SAME clock signal SIMULTANEOUSLY — faster, more complex circuitry

JRF-level numericalAn n-bit binary counter can count from 0 to 2^n−1, a total of 2^n distinct states. A MOD-12 counter (counts 0 to 11) needs at least ⌈log2(12)⌉ = 4 flip-flops (since 2^3=8<12≤2^4=16). This "minimum flip-flops for a MOD-N counter" numerical is frequently tested.

MUST REMEMBER — Chapter 1

• Half Adder: no carry-in (Sum=A⊕B, Carry=AB). Full Adder: has carry-in, needed for multi-bit chains.
• MUX: n-to-1 needs log2(n) select lines; k select lines give 2^k inputs. DEMUX does the reverse of MUX.
• Decoder: n inputs → up to 2^n outputs. Encoder: 2^n inputs → n outputs (needs Priority Encoder if multiple inputs active).
• SR flip-flop: S=R=1 is invalid. JK flip-flop: fixes this — J=K=1 causes TOGGLE instead. D flip-flop: Q_next=D (no invalid state). T flip-flop: toggles when T=1.
• MOD-N counter needs ⌈log2(N)⌉ flip-flops minimum. Asynchronous(ripple)=sequential triggering,slower; Synchronous=simultaneous triggering,faster.

DON'T CONFUSE

• Half Adder (no carry-in) vs Full Adder (has carry-in, needed for chains).
• Decoder (few→many outputs) vs Encoder (many→few outputs) — opposite directions.
• SR flip-flop (invalid state at S=R=1) vs JK flip-flop (toggles instead, no invalid state).

JRF CHALLENGE ZONE — Chapter 1

1. How many select lines does a 64-to-1 MUX require?
Answer: log2(64) = 6

2. Which flip-flop has NO invalid/undefined input combination? (a) SR (b) JK (c) D (d) Both (b) and (c)
Answer: (d)

3. Minimum number of flip-flops needed for a MOD-20 counter?
Answer: ⌈log2(20)⌉ = 5 (since 2⁴=16<20≤2⁵=32)

Practice Questions — Chapter 1 (8)

1. Write the Sum and Carry equations for a Half Adder.
   Ans: Sum=A⊕B, Carry=A·B
2. Why can't a Half Adder be chained to build a multi-bit adder?
   Ans: It has no carry-in input, needed to accept the carry from the previous stage
3. How many select lines does an 8-to-1 MUX need?
   Ans: log2(8)=3
4. Differentiate a Decoder and an Encoder.
   Ans: A decoder converts n inputs into up to 2ⁿ outputs; an encoder does the reverse, converting 2ⁿ inputs into n outputs
5. Why is a Priority Encoder needed over a basic Encoder?
   Ans: A basic encoder gives ambiguous output if multiple inputs are active simultaneously; a priority encoder resolves this by prioritizing one input
6. What is the invalid state of an SR flip-flop, and how does a JK flip-flop resolve it?
   Ans: S=R=1 is invalid in SR; JK resolves it by making J=K=1 cause a toggle instead
7. Differentiate an Asynchronous (ripple) counter and a Synchronous counter.
   Ans: Asynchronous counters trigger flip-flops sequentially (slower, delay accumulates); synchronous counters trigger all flip-flops simultaneously with the same clock (faster)
8. Minimum flip-flops needed for a MOD-6 counter?
   Ans: ⌈log2(6)⌉=3 (since 2²=4<6≤2³=8)

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Chapter 2 — Data Representation

2.1 Signed Number Representations

Representation	Idea	Range (n bits)
Sign-Magnitude	1 bit for sign, rest for magnitude	−(2^(n−1)−1) to +(2^(n−1)−1)
1's Complement	Negative = flip ALL bits of positive	−(2^(n−1)−1) to +(2^(n−1)−1)
2's Complement	Negative = flip all bits, then ADD 1	−2^(n−1) to +(2^(n−1)−1)

JRF trap — TWO zeros vs ONE zeroSign-Magnitude and 1's Complement BOTH have TWO representations of zero (+0 and −0) — this wastes one code and complicates arithmetic circuit design. 2's Complement has only ONE representation of zero, and its range is ASYMMETRIC (one extra negative number, since there's no wasted second-zero code) — THIS is exactly why 2's Complement is used in virtually ALL modern computer hardware. This "why 2's complement won" reasoning is a very frequently tested JRF concept.

Worked example — 2's complementRepresent −5 in 8-bit 2's complement. +5 = 00000101. Flip all bits: 11111010. Add 1: 11111011. Verify: this is −5 since 11111011 = −(00000101)+1's-complement-trick... standard check: treat as unsigned (251), 251−256=−5 ✓.

2.2 Binary Arithmetic — 2's Complement Addition/Subtraction

JRF-level numericalCompute 5 + (−3) using 8-bit 2's complement. +5 = 00000101. −3 in 2's complement: +3=00000011, flip=11111100, +1=11111101. Add: 00000101 + 11111101 = 100000010 → DISCARD the overflow carry bit (9th bit) → 00000010 = +2 ✓ (5−3=2, correct).

Trap — overflow detectionIn 2's complement addition, OVERFLOW occurs ONLY when adding TWO NUMBERS OF THE SAME SIGN produces a result with the OPPOSITE sign (e.g., adding two positives gives a negative result, or two negatives give a positive result). Adding numbers of DIFFERENT signs can NEVER cause overflow. This precise overflow-detection rule is a classic JRF numerical trap.

2.3 Floating Point Representation (IEEE 754)

Format	Total Bits	Sign	Exponent	Mantissa
Single Precision	32	1	8 (bias=127)	23
Double Precision	64	1	11 (bias=1023)	52

Value = (−1)^sign × 1.mantissa × 2^(exponent−bias)

JRF-level numericalRepresent 10.25 in IEEE 754 single precision. 10.25 in binary = 1010.01. Normalize: 1.01001 × 2^3. Sign=0 (positive). Exponent = 3+127(bias) = 130 = 10000010. Mantissa (23 bits, drop the leading 1) = 01001000000000000000000. Final: 0 | 10000010 | 01001000000000000000000. This "normalize → add bias to exponent → extract mantissa bits" procedure is THE standard IEEE 754 JRF numerical.

NET pointThe BIAS is added to the actual exponent specifically so the STORED exponent field is always NON-NEGATIVE (unsigned), avoiding the need for a separate sign bit for the exponent itself — this simplifies comparing floating-point numbers using ordinary unsigned integer comparison circuits.

2.4 BCD & Gray Code (Brief)

IdeaBCD (Binary Coded Decimal) encodes EACH decimal digit separately as its own 4-bit binary value (e.g., 25 in BCD = 0010 0101, NOT the pure-binary 11001) — easier for decimal I/O (displays, decimal arithmetic) but wastes some bit patterns (1010–1111 are invalid/unused in BCD). Gray Code changes only ONE bit between consecutive values — used to avoid glitches in circuits like rotary encoders, where multiple simultaneous bit changes could cause a transient incorrect reading.

MUST REMEMBER — Chapter 2

• Sign-magnitude & 1's complement: TWO zeros (+0,−0), symmetric range. 2's complement: ONE zero, asymmetric range (extra negative number).
• 2's complement is used in hardware because of the single-zero + simpler arithmetic circuit design.
• 2's complement negation: flip all bits, then add 1.
• Overflow in 2's complement addition occurs ONLY when adding same-signed numbers gives an opposite-signed result.
• IEEE 754 single precision: 1 sign + 8 exponent(bias 127) + 23 mantissa bits = 32 total. Double: 1+11(bias 1023)+52=64.
• Value = (−1)^sign × 1.mantissa × 2^(exponent−bias).
• BCD: each decimal digit → separate 4 bits. Gray code: only 1 bit changes between consecutive values.

DON'T CONFUSE

• 1's complement (flip bits only) vs 2's complement (flip bits, then add 1).
• BCD (each digit encoded separately) vs pure binary (whole number encoded together).

JRF CHALLENGE ZONE — Chapter 2

1. In n-bit 2's complement, what is the range? (a) −2^(n−1) to +2^(n−1) (b) −2^(n−1) to +(2^(n−1)−1) (c) −(2^(n−1)−1) to +(2^(n−1)−1) (d) 0 to 2^n−1
Answer: (b)

2. Adding two POSITIVE 8-bit 2's complement numbers produces a NEGATIVE result. This indicates: (a) Correct result (b) Overflow (c) Underflow (d) An invalid operation, impossible to occur
Answer: (b)

3. In IEEE 754 single precision, what is the exponent bias?
Answer: 127

Practice Questions — Chapter 2 (8)

1. Why does 2's complement have only ONE representation of zero?
   Ans: Because negation (flip bits, add 1) applied to zero wraps back to the same all-zero pattern, unlike sign-magnitude/1's complement which have separate +0 and −0
2. Represent −7 in 8-bit 2's complement.
   Ans: +7=00000111; flip=11111000; +1=11111001
3. State the overflow-detection rule for 2's complement addition.
   Ans: Overflow occurs only when adding two same-signed numbers produces a result with the opposite sign
4. How many total bits, and how many mantissa bits, does IEEE 754 single precision use?
   Ans: 32 total bits; 23 mantissa bits
5. What is the exponent bias for IEEE 754 double precision?
   Ans: 1023
6. Why is a bias added to the floating-point exponent rather than storing it as a signed value?
   Ans: So the stored exponent is always non-negative, simplifying comparison using unsigned integer circuits
7. How does BCD encode the decimal number 47?
   Ans: 0100 0111 (4 as 0100, 7 as 0111 — each digit separately in 4 bits)
8. Why is Gray Code useful in rotary encoders?
   Ans: Only one bit changes between consecutive values, avoiding glitches from multiple simultaneous bit transitions

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Chapter 3 — Register Transfer & Microoperations

3.1 Register Transfer Language (RTL)

IdeaRTL provides symbolic notation to describe micro-level data movement between registers: R2 ← R1 means "transfer the contents of R1 INTO R2" (the ORIGINAL contents of R1 remain UNCHANGED — this is a COPY, not a move).

JRF trapA conditional transfer is written as: P: R2 ← R1 (meaning "IF control signal P=1 THEN R2←R1 during THIS clock pulse"). Students often forget that the control condition (P) is evaluated BEFORE/DURING the SAME clock edge — the transfer is NOT delayed to a later cycle.

3.2 Bus & Memory Transfer

IdeaA common BUS system (using multiplexers) allows MULTIPLE registers to share the SAME set of transfer lines — reduces the number of physical wires needed, at the cost of only ONE transfer being possible at a time over that bus.

Memory read: R ← M[AR] (AR=Address Register) Memory write: M[AR] ← R

3.3 Types of Microoperations

Type	Examples
Register Transfer	R2 ← R1 (simple copy between registers)
Arithmetic	R3 ← R1+R2, R2 ← R2+1 (increment), R2 ← R2' (complement)
Logic	R1 ← R1 AND R2, R1 ← R1 OR R2, R1 ← R1 XOR R2
Shift	Logical shift (fills with 0), Circular shift (wraps around), Arithmetic shift (preserves sign bit)

JRF trap — logical vs arithmetic shiftA LOGICAL right shift always fills the vacated leftmost bit with 0 (treats the number as unsigned). An ARITHMETIC right shift fills the vacated leftmost bit with a COPY of the ORIGINAL SIGN BIT (preserving the sign, effectively performing division by 2 for signed numbers, rounding toward negative infinity). Applying a logical shift to a NEGATIVE signed number would incorrectly change its sign — this is exactly why arithmetic shift exists separately. This distinction is one of the most frequently tested microoperation facts.

MUST REMEMBER — Chapter 3

• R2←R1 is a COPY (R1 unchanged), not a destructive move.
• Conditional transfer "P: R2←R1" happens during the SAME clock pulse if P=1, not delayed.
• 4 microoperation types: Register Transfer, Arithmetic, Logic, Shift.
• Logical shift: fills with 0 (unsigned). Arithmetic shift: fills with sign bit copy (preserves sign for signed numbers).
• Circular shift: bit shifted out re-enters on the other end (wraps around).

DON'T CONFUSE

• Logical shift (fills with 0) vs Arithmetic shift (fills with sign bit) vs Circular shift (wraps around).
• R2←R1 (copy, non-destructive to R1) — a common misconception is thinking R1 gets cleared.

JRF CHALLENGE ZONE — Chapter 3

1. After executing R2 ← R1, what happens to R1's original contents? (a) Cleared to 0 (b) Unchanged (c) Swapped with R2 (d) Undefined
Answer: (b)

2. An arithmetic right shift on a negative number fills the leftmost bit with: (a) Always 0 (b) Always 1 (c) A copy of the original sign bit (d) A random value
Answer: (c)

Practice Questions — Chapter 3 (6)

1. What does the RTL statement R3 ← R1 + R2 mean?
   Ans: Add the contents of R1 and R2, and store the result in R3
2. What does "P: R2 ← R1" mean in RTL notation?
   Ans: If control signal P=1, transfer R1 into R2 during that clock pulse
3. Why does a shared bus system reduce wiring, and what is its limitation?
   Ans: Multiple registers share the same lines, reducing wire count; the limitation is only one transfer can happen at a time over the bus
4. List the four types of microoperations.
   Ans: Register transfer, arithmetic, logic, shift
5. Differentiate a logical shift and an arithmetic shift.
   Ans: Logical shift fills the vacated bit with 0; arithmetic shift fills it with a copy of the sign bit, preserving the number's sign
6. Why is a logical shift unsuitable for shifting a negative signed number?
   Ans: It fills with 0 regardless of sign, which can incorrectly change a negative number to appear positive

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Chapter 4 — Basic Computer Organization & Design

4.1 Instruction Format & Addressing Modes

IdeaA basic instruction typically has: Opcode (operation to perform) + Address field (operand location) + Mode bit (indicates direct or indirect addressing).

Addressing Mode	Idea
Direct	Address field gives the OPERAND'S address directly
Indirect	Address field gives the address of a MEMORY LOCATION that itself CONTAINS the operand's address (one extra memory access needed)
Immediate	The OPERAND ITSELF is given directly in the instruction (no memory access needed to fetch it)
Register	Address field specifies a REGISTER holding the operand (fast, no memory access)

JRF trapIndirect addressing requires an EXTRA memory access compared to direct addressing (fetch the pointer, THEN fetch the actual operand) — slower, but allows accessing a much LARGER effective address space using a small address field (since the full address is stored in memory, not limited by instruction bit-width). "Indirect = one extra memory reference, but larger addressable range" is a classic tradeoff fact.

4.2 Instruction Cycle

Fetch instruction (from memory, using PC) → Decode instruction (determine opcode/operands) → Determine effective address (if indirect) → Fetch operands → Execute instruction → (check for interrupt) → repeat

JRF trap — timing/control signals (T-states)Each step of the instruction cycle is controlled by a SEQUENCE COUNTER generating timing signals T0, T1, T2... A classic exam question traces WHICH register-transfer microoperations happen at EACH T-state (e.g., T0: AR←PC; T1: IR←M[AR], PC←PC+1; T2: decode opcode from IR). Knowing this exact fetch-cycle micro-operation sequence is frequently tested.

4.3 Interrupt Cycle

IdeaWhen an interrupt occurs (after completing the current instruction, interrupt flag checked), the CPU must: (1) SAVE the return address (current PC) — typically to a fixed memory location or a stack, (2) branch to the Interrupt Service Routine (ISR), (3) after the ISR completes, RESTORE the saved PC to resume the interrupted program.

MUST REMEMBER — Chapter 4

• Direct addressing: address field = operand's address. Indirect: address field → pointer → operand (extra memory access, larger effective range).
• Immediate: operand is IN the instruction itself (fastest, no memory fetch for operand). Register: operand is in a register (fast, no memory access).
• Instruction cycle: Fetch → Decode → (Determine effective address if indirect) → Fetch operands → Execute → check interrupt.
• Interrupt cycle: save PC (return address) → branch to ISR → restore PC after ISR completes.

DON'T CONFUSE

• Direct addressing (address field = operand address) vs Indirect addressing (address field = pointer to the operand address).
• Immediate addressing (operand IN instruction) vs Direct addressing (operand's ADDRESS in instruction).

JRF CHALLENGE ZONE — Chapter 4

1. Which addressing mode requires an EXTRA memory access compared to direct addressing? (a) Immediate (b) Register (c) Indirect (d) None
Answer: (c)

2. During an interrupt, what must the CPU save before branching to the ISR? (a) The data registers only (b) The return address (PC) (c) Nothing needs saving (d) The interrupt vector only
Answer: (b)

Practice Questions — Chapter 4 (6)

1. Differentiate direct and indirect addressing.
   Ans: Direct: address field holds the operand's address; Indirect: address field holds the address of a location that itself holds the operand's address
2. Why does indirect addressing allow access to a larger effective address space?
   Ans: The full address is stored in memory, not limited by the instruction's smaller address field width
3. What is the tradeoff of indirect addressing compared to direct addressing?
   Ans: It requires one extra memory access, making it slower
4. List the main steps of the instruction cycle in order.
   Ans: Fetch, decode, determine effective address (if indirect), fetch operands, execute, check for interrupt
5. What must the CPU do first when handling an interrupt?
   Ans: Save the return address (current PC)
6. What happens after an Interrupt Service Routine (ISR) finishes?
   Ans: The saved PC is restored, resuming the interrupted program

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Chapter 5 — Programming the Basic Computer

5.1 Machine Language vs Assembly Language

	Machine Language	Assembly Language
Form	Raw binary opcodes/operands	Human-readable mnemonics (e.g., ADD, LDA)
Needs translation?	No — directly executable by hardware	Yes — needs an Assembler to convert to machine code

5.2 Assembler — One-Pass vs Two-Pass

IdeaA ONE-PASS assembler processes the source code in a single scan — struggles with FORWARD REFERENCES (a label used before it's defined later in the code). A TWO-PASS assembler scans TWICE: Pass 1 builds the symbol table (records every label's address); Pass 2 generates the actual machine code, now able to resolve ALL references (forward or backward) correctly.

JRF trapThe fundamental REASON two-pass assembly exists is to handle FORWARD REFERENCES correctly — a one-pass assembler encountering a forward-referenced label doesn't yet know its address, requiring complicated "backpatching" workarounds; two-pass assembly avoids this entirely by building the COMPLETE symbol table first (Pass 1) before generating any code (Pass 2). "Why do we need two passes" is a classic JRF conceptual question.

5.3 Subroutines

IdeaA subroutine is a reusable block of code, called from multiple places in a program. Calling a subroutine requires saving the RETURN ADDRESS (so execution can resume correctly afterward) — typically using a STACK, which naturally supports NESTED subroutine calls (each call pushes a new return address; each return pops the most recent one, in LIFO order).

JRF trapA Stack is the natural choice for managing subroutine return addresses specifically because subroutine calls can NEST (a subroutine calling another subroutine) — the LIFO (Last-In-First-Out) property of a stack EXACTLY matches the requirement that the MOST RECENTLY called subroutine must be the FIRST to return. Using a simple fixed memory location (instead of a stack) would break for nested/recursive calls.

MUST REMEMBER — Chapter 5

• Machine language = raw binary, directly executable. Assembly language = mnemonics, needs an Assembler.
• One-pass assembler: struggles with forward references. Two-pass: Pass 1 builds symbol table, Pass 2 generates code (handles forward refs correctly).
• Subroutine return addresses are managed via a Stack (LIFO) — naturally supports nested/recursive calls.

DON'T CONFUSE

• One-pass assembler (struggles with forward references) vs Two-pass assembler (resolves them cleanly via symbol table).

JRF CHALLENGE ZONE — Chapter 5

1. What problem does a two-pass assembler specifically solve, that a one-pass assembler struggles with? (a) Syntax errors (b) Forward references (c) Comment parsing (d) Nothing, they're identical
Answer: (b)

2. Why is a Stack (not a fixed memory location) used to store subroutine return addresses? (a) It's faster (b) It naturally supports nested/recursive calls via LIFO order (c) It uses less memory (d) No particular reason
Answer: (b)

Practice Questions — Chapter 5 (5)

1. Differentiate machine language and assembly language.
   Ans: Machine language is raw binary, directly executable; assembly language uses human-readable mnemonics and needs an assembler to convert to machine code
2. What does Pass 1 of a two-pass assembler do?
   Ans: Builds the symbol table, recording the address of every label
3. What does Pass 2 of a two-pass assembler do?
   Ans: Generates the actual machine code, now able to resolve all label references
4. What is a "forward reference" in assembly programming?
   Ans: A label used in code before it has been defined later in the program
5. Why is a stack well-suited for managing subroutine return addresses?
   Ans: Its LIFO order matches the requirement that the most recently called subroutine returns first, supporting nesting

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Chapter 6 — Central Processing Unit

6.1 Instruction Formats by Address Count

Format	Idea	Example (A=B+C)
Three-address	Two source operands + one destination, all explicit	ADD A,B,C (A=B+C)
Two-address	One operand doubles as source AND destination	MOV A,B then ADD A,C
One-address	Uses an implied ACCUMULATOR as the other operand/destination	LOAD B; ADD C; STORE A
Zero-address (Stack)	Operands implicitly taken from the TOP of a stack	PUSH B; PUSH C; ADD; POP A

JRF trapFewer address fields per instruction (e.g., one-address, zero-address) generally means SHORTER instructions (saves memory/bandwidth) but requires MORE instructions to accomplish the same task (more total instructions fetched/executed) — a classic space-vs-instruction-count tradeoff. Zero-address (stack-based) architecture is exactly why Reverse Polish (postfix) notation is convenient for expression evaluation — operands are naturally pushed, operators naturally pop and compute.

6.2 RISC vs CISC

	RISC	CISC
Instruction set	Small, SIMPLE instructions	Large, COMPLEX instructions (can do more per instruction)
Instruction size	Fixed length	Variable length
Execution	Mostly single-cycle (1 clock per instruction), pipeline-friendly	Multiple cycles per instruction (variable)
Memory access	ONLY via LOAD/STORE instructions (register-based ALU ops)	ALU instructions can directly access memory
Compiler complexity	MORE complex compiler (must generate more instructions)	Simpler compiler (fewer, richer instructions to choose from)

JRF trap — the load/store restrictionRISC's "Load/Store architecture" means ONLY dedicated LOAD and STORE instructions can access memory — ALL arithmetic/logic instructions operate PURELY on registers, never touching memory directly. This restriction is exactly what makes RISC instructions uniform/simple enough for efficient pipelining. CISC allows an ALU instruction (e.g., ADD) to directly read/write memory in a single instruction, which is more "compact" per instruction but harder to pipeline efficiently. This load/store distinction is THE most tested RISC-vs-CISC fact.

6.3 Stack Organization

IdeaA hardware stack uses a Stack Pointer (SP) register tracking the current TOP of the stack. PUSH decrements/increments SP then writes; POP reads then increments/decrements SP (direction depends on whether the stack grows toward higher or lower memory addresses).

JRF-level numerical — postfix evaluation using a stackEvaluate postfix expression: 6 3 2 + * (using a stack). Push 6: [6]. Push 3: [6,3]. Push 2: [6,3,2]. Operator '+': pop 2,3 → 3+2=5, push 5: [6,5]. Operator '*': pop 5,6 → 6*5=30, push 30: [30]. Final result = 30. This "trace the stack contents step by step through a postfix expression" is THE standard stack-organization JRF numerical.

MUST REMEMBER — Chapter 6

• Instruction formats: 3-address(explicit)→2-address→1-address(accumulator)→0-address(stack) — fewer addresses = shorter instructions but MORE instructions needed.
• RISC: simple, fixed-length, single-cycle, Load/Store ONLY memory access, complex compiler.
• CISC: complex, variable-length, multi-cycle, ALU can access memory directly, simpler compiler.
• RISC's Load/Store restriction is what enables efficient pipelining.
• Postfix evaluation: push operands; on an operator, pop the required operands, compute, push result back.

DON'T CONFUSE

• RISC (Load/Store only, memory NEVER touched by ALU ops) vs CISC (ALU instructions CAN access memory directly).
• Fewer address fields = shorter instructions, but MORE total instructions needed (not simply "better").

JRF CHALLENGE ZONE — Chapter 6

1. Which architecture restricts memory access to ONLY dedicated Load/Store instructions? (a) CISC (b) RISC (c) Both equally (d) Neither
Answer: (b)

2. Evaluate postfix: 5 1 2 + 4 * + (using a stack).
Answer: Push5,1,2→[5,1,2]. '+'→pop2,1→3,push→[5,3]. Push4→[5,3,4]. '*'→pop4,3→12,push→[5,12]. '+'→pop12,5→17,push→[17]. Result=17.

Practice Questions — Chapter 6 (7)

1. Write a three-address instruction for A=B+C.
   Ans: ADD A,B,C
2. What is the tradeoff of using fewer address fields per instruction?
   Ans: Shorter/smaller instructions, but more total instructions needed to accomplish the same task
3. Differentiate RISC and CISC in terms of instruction complexity.
   Ans: RISC uses small, simple, fixed-length instructions; CISC uses larger, complex, variable-length instructions
4. What is RISC's "Load/Store" restriction?
   Ans: Only dedicated Load/Store instructions can access memory; all ALU operations work purely on registers
5. Why does RISC's Load/Store restriction help with pipelining?
   Ans: It keeps instructions uniform and simple, making them easier to overlap in a pipeline
6. Evaluate postfix expression 4 5 + 2 * using a stack.
   Ans: Push4,5→[4,5]. '+'→9→[9]. Push2→[9,2]. '*'→18→[18]. Result=18
7. What register tracks the current top of a hardware stack?
   Ans: Stack Pointer (SP)

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Chapter 7 — Pipelining

7.1 Pipelining — Basic Idea

SimplePipelining overlaps EXECUTION of multiple instructions across different STAGES (like an assembly line) — while one instruction is being decoded, the next can already be fetched, dramatically increasing THROUGHPUT (instructions completed per unit time), though NOT reducing any single instruction's individual LATENCY.

7.2 Pipeline Speedup — Numerical

Ideal Speedup (k-stage pipeline, n instructions) = n×k / (k + (n−1)) As n→∞, Speedup approaches k (the number of stages)

JRF-level numericalA 4-stage pipeline (k=4) executes 100 instructions (n=100). Without pipelining: time = n×k = 400 cycles (each instruction takes all 4 stages sequentially, one at a time). WITH pipelining: time = k + (n−1) = 4+99 = 103 cycles. Speedup = 400/103 ≈ 3.88. This "compute both non-pipelined and pipelined total cycles, then divide" technique is THE standard pipeline speedup JRF numerical.

7.3 Pipeline Hazards

Hazard Type	Cause	Example Fix
Structural Hazard	Two instructions need the SAME hardware resource simultaneously (e.g., one memory unit for both instruction fetch and data access)	Duplicate hardware (e.g., separate instruction/data memory)
Data Hazard	An instruction needs a result that a PREVIOUS instruction hasn't finished computing yet	Forwarding/bypassing, or pipeline stall
Control Hazard	A BRANCH instruction — the pipeline doesn't know WHICH instruction to fetch next until the branch is resolved	Branch prediction, delayed branching

JRF trap — data hazard types (RAW/WAR/WAW)RAW (Read After Write) is the TRUE/genuine data hazard — an instruction tries to READ a value BEFORE a previous instruction has WRITTEN it. WAR (Write After Read) and WAW (Write After Write) are called "FALSE" hazards — they only arise from REUSING the same register name/location, not from any real dependency, and can be eliminated via register renaming. Confusing genuine (RAW) vs name-based/false (WAR, WAW) hazards is a frequently tested JRF distinction.

NET pointFORWARDING (also called bypassing) solves MANY data hazards WITHOUT stalling — it routes a computed result DIRECTLY from one pipeline stage to an earlier stage that needs it, instead of waiting for the result to be formally written back to the register file first. Forwarding can't help if the needed value simply isn't computed yet at all (e.g., a LOAD followed immediately by an instruction using that loaded value) — this specific case still requires a stall (a "load-use hazard").

MUST REMEMBER — Chapter 7

• Pipelining improves THROUGHPUT, not individual instruction LATENCY.
• Pipelined time = k+(n−1); non-pipelined time = n×k. Speedup = (n×k)/(k+(n−1)), approaches k as n grows.
• 3 hazard types: Structural(resource conflict), Data(value not ready yet), Control(branch outcome unknown).
• RAW = true/genuine data hazard. WAR, WAW = false/name-based hazards (fixable via register renaming).
• Forwarding/bypassing avoids many stalls, but a load-use hazard still needs a stall (value not computed in time).

DON'T CONFUSE

• RAW (genuine/true hazard) vs WAR/WAW (false, name-based hazards, fixable by renaming).
• Structural hazard (hardware resource conflict) vs Data hazard (value dependency) vs Control hazard (branch uncertainty).

JRF CHALLENGE ZONE — Chapter 7

1. A 5-stage pipeline executes 50 instructions. Find the pipelined execution time in cycles.
Answer: k+(n−1) = 5+49 = 54

2. Which hazard type is considered a "false" hazard, fixable by register renaming? (a) RAW (b) Structural (c) WAR/WAW (d) Control
Answer: (c)

3. Does pipelining reduce the time taken to complete a SINGLE instruction (latency)? (a) Yes, always (b) No — it improves throughput, not individual latency (c) Only for RISC (d) Only with forwarding
Answer: (b)

Practice Questions — Chapter 7 (7)

1. Does pipelining improve throughput, latency, or both?
   Ans: Throughput — not individual instruction latency
2. A 6-stage pipeline processes 20 instructions. Find pipelined execution time.
   Ans: k+(n−1) = 6+19 = 25 cycles
3. What causes a Structural Hazard? Give an example.
   Ans: Two instructions competing for the same hardware resource, e.g., a single memory unit needed for both instruction fetch and data access simultaneously
4. What causes a Control Hazard?
   Ans: A branch instruction, where the next instruction to fetch is unknown until the branch is resolved
5. Differentiate a RAW hazard from WAR/WAW hazards.
   Ans: RAW is a genuine data dependency (reading before a write completes); WAR/WAW are false hazards caused by register reuse, fixable via renaming
6. What does "forwarding" (bypassing) do to help with data hazards?
   Ans: Routes a computed result directly to an earlier pipeline stage that needs it, without waiting for register write-back
7. Why can't forwarding alone solve a load-use hazard?
   Ans: The loaded value simply isn't available yet at the time the next instruction needs it, requiring a stall regardless

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Chapter 8 — Memory Hierarchy & Cache Mapping

8.1 Memory Hierarchy — Overview

SimpleMemory is organized in a hierarchy trading off SPEED vs SIZE vs COST: Registers (fastest, smallest, most expensive per bit) → Cache → Main Memory (RAM) → Secondary Storage (disk, slowest, largest, cheapest per bit).

NET pointThe hierarchy works because of LOCALITY OF REFERENCE: Temporal locality (recently accessed data is likely to be accessed again soon) and Spatial locality (data near a recently accessed location is likely to be accessed soon too) — caching exploits BOTH by keeping recently-used AND nearby data close to the CPU.

8.2 Cache Performance — Hit Ratio & AAT

Hit Ratio (h) = Cache hits / Total memory accesses Average Access Time (AAT) = h × Cache_time + (1−h) × Memory_time (for a "hit-then-miss-penalty" model: AAT = Cache_time + (1−h) × Miss_penalty)

JRF-level numericalCache access time = 10ns, Main memory access time = 100ns, Hit ratio = 0.9. AAT = 0.9×10 + 0.1×100 = 9+10 = 19ns. This exact weighted-average calculation is THE standard cache-performance JRF numerical. Note: some formulations use AAT = Cache_time + (1−h)×Memory_time (treating cache time as always paid) — always check which formula variant a given question intends, since results differ slightly.

8.3 Cache Mapping Techniques

Mapping	Idea
Direct Mapping	Each main memory block maps to EXACTLY ONE specific cache line (via block-address mod number-of-lines) — simple/fast, but causes frequent CONFLICTS (two blocks mapping to the same line evict each other repeatedly, even if other cache lines are free)
Fully Associative Mapping	A block can go into ANY cache line — no conflict misses, but needs to SEARCH ALL lines simultaneously (expensive comparator hardware) and complex replacement policy needed
Set-Associative Mapping	A middle ground: cache divided into SETS, each holding k lines ("k-way set-associative") — a block maps to one SPECIFIC SET, but can go in ANY of the k lines within that set

JRF-level numerical — direct mappingCache has 128 lines, main memory has 8192 blocks. Using direct mapping, which cache line does memory block 300 map to? Cache line = block number mod number of cache lines = 300 mod 128 = 44. This "block mod cache-line-count" calculation is THE fundamental direct-mapping JRF numerical.

JRF trap — direct mapping conflictIn Direct Mapping, blocks 44, 172 (44+128), 300 (44+256), etc. ALL map to the SAME cache line 44 — even if every OTHER cache line is completely empty, repeatedly accessing blocks 44 and 172 alternately causes CONSTANT eviction/re-loading ("thrashing"), because Direct Mapping allows NO flexibility in placement. This is exactly the weakness that Set-Associative mapping addresses.

8.4 Replacement Policies (for Associative/Set-Associative Caches)

Policy	Idea
LRU (Least Recently Used)	Evicts the line NOT used for the LONGEST time — good locality-based approximation, but needs tracking overhead
FIFO	Evicts the OLDEST-LOADED line, regardless of recent usage
Random	Evicts a RANDOMLY chosen line — simple hardware, surprisingly competitive performance

8.5 Write Policies

Policy	Idea
Write-Through	Every write updates BOTH cache AND main memory IMMEDIATELY — simpler, always consistent, but SLOWER (every write pays main-memory latency)
Write-Back	Write updates ONLY the cache; main memory is updated LATER, only when that cache line is evicted ("dirty bit" marks it as needing write-back) — FASTER, but more complex, and data can be temporarily inconsistent between cache/memory

MUST REMEMBER — Chapter 8

• Memory hierarchy: Registers→Cache→RAM→Disk, trading speed for size/cost. Works due to Temporal + Spatial locality.
• AAT = h×Cache_time + (1−h)×Memory_time (or Cache_time+(1−h)×Miss_penalty, depending on model).
• Direct mapping: block mod (number of cache lines) = target line; simple but conflict-prone (thrashing risk).
• Fully associative: any line, no conflicts, but expensive hardware search. Set-associative: middle ground (k-way).
• LRU=evict least-recently-used; FIFO=evict oldest-loaded; Random=evict randomly.
• Write-through: updates memory immediately (slower, always consistent). Write-back: updates memory only on eviction (faster, needs dirty bit).

DON'T CONFUSE

• Direct mapping (one specific line, conflict-prone) vs Fully associative (any line, no conflicts) vs Set-associative (middle ground).
• Write-through (immediate memory update) vs Write-back (delayed update on eviction, uses dirty bit).

JRF CHALLENGE ZONE — Chapter 8

1. Cache access=5ns, memory access=80ns, hit ratio=0.95. Find AAT (using AAT=h×Cache+(1−h)×Memory).
Answer: 0.95×5+0.05×80 = 4.75+4 = 8.75ns

2. Cache has 64 lines. Using direct mapping, which line does memory block 250 map to?
Answer: 250 mod 64 = 58

3. Which mapping technique allows a block to be placed in ANY cache line? (a) Direct (b) Fully Associative (c) Both equally (d) Neither
Answer: (b)

Practice Questions — Chapter 8 (8)

1. List the memory hierarchy levels from fastest/smallest to slowest/largest.
   Ans: Registers, Cache, Main Memory (RAM), Secondary Storage (disk)
2. What two types of locality does caching exploit?
   Ans: Temporal locality and Spatial locality
3. Cache time=8ns, memory time=120ns, hit ratio=0.85. Find AAT.
   Ans: 0.85×8+0.15×120 = 6.8+18 = 24.8ns
4. Cache has 256 lines. Using direct mapping, which line does memory block 900 map to?
   Ans: 900 mod 256 = 132
5. What is the main weakness of Direct Mapping?
   Ans: Conflict misses/thrashing — blocks mapping to the same line repeatedly evict each other even if other lines are free
6. Differentiate Fully Associative and Set-Associative mapping.
   Ans: Fully associative allows a block anywhere in the cache; set-associative restricts it to one specific set, but allows any line within that set
7. Differentiate Write-Through and Write-Back policies.
   Ans: Write-through updates memory immediately on every write; write-back updates memory only when the cache line is evicted, using a dirty bit
8. What does a "dirty bit" indicate in a write-back cache?
   Ans: That the cache line has been modified and needs to be written back to memory before eviction

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One-Shot Revision — Unit 10

Key facts across all chapters

• Half Adder: no carry-in. Full Adder: has carry-in, needed for chains. MUX: log2(n) select lines for n-to-1.
• Decoder: n→up to 2ⁿ outputs. Encoder: 2ⁿ→n (needs Priority Encoder for multiple active inputs).
• SR: S=R=1 invalid. JK: fixes it via toggle. D: Q_next=D. T: toggles when T=1. MOD-N counter needs ⌈log2 N⌉ flip-flops.
• 2's complement: ONE zero, flip+add1 for negation; used in hardware. Overflow: same-sign addends → opposite-sign result.
• IEEE754 single: 1+8(bias127)+23=32 bits. Double: 1+11(bias1023)+52=64 bits. Value=(−1)^s×1.mantissa×2^(exp−bias).
• R2←R1 is a copy (R1 unchanged). Logical shift: fills 0. Arithmetic shift: fills sign-bit copy. Circular: wraps around.
• Direct addressing: address=operand address. Indirect: address→pointer→operand (extra access, larger range). Immediate: operand IN instruction.
• Instruction cycle: Fetch→Decode→(effective address if indirect)→Fetch operands→Execute→check interrupt.
• Two-pass assembler: Pass1=symbol table, Pass2=code generation (solves forward references).
• Stack for subroutines: LIFO matches nested call/return order.
• 3-address→2-address→1-address(accumulator)→0-address(stack): fewer addresses=shorter instructions,more total instructions.
• RISC: simple,fixed-length,single-cycle,Load/Store ONLY memory access. CISC: complex,variable-length,multi-cycle,ALU can access memory.
• Pipelining improves throughput not latency. Pipelined time=k+(n−1); Speedup=(n×k)/(k+(n−1)).
• Hazards: Structural(resource conflict), Data(RAW=true;WAR/WAW=false/renameable), Control(branch). Forwarding avoids most stalls except load-use.
• Memory hierarchy: Registers→Cache→RAM→Disk (locality of reference: temporal+spatial).
• AAT=h×Cache+(1−h)×Memory. Direct mapping: block mod lines. Fully associative: any line. Set-associative: middle ground.
• Write-through: immediate memory update. Write-back: update on eviction only, uses dirty bit.

Potential future exam areasPotential high-value exam area based on syllabus importance and historical question patterns: MUX/counter select-line and flip-flop-count numericals; 2's complement addition with overflow detection; IEEE 754 encode/decode numericals; addressing-mode tradeoff scenario questions; RISC-vs-CISC load/store distinguishing questions; postfix-expression stack-evaluation traces; pipeline speedup and hazard-type identification numericals; and direct-mapping cache-line numericals combined with AAT calculations.

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Unit 10 — UGC NET/JRF Mini Mock Test

45 questions across all 8 chapters. NTA/UGC NET-style question patterns — mixed NET/JRF difficulty, numerical, statement-based, matching and scenario-based. Answer key with brief explanations follows each question.

Q1. How many select lines does a 16-to-1 MUX require?
Ans: log2(16)=4 [Ch1 | NET numerical]

Q2. Which flip-flop has an invalid/undefined state? (a) D (b) T (c) SR (d) JK
Ans: (c) [Ch1 | NET]

Q3. Minimum flip-flops needed for a MOD-10 counter?
Ans: ⌈log2(10)⌉=4 [Ch1 | NET numerical]

Q4. Which number representation has only ONE zero? (a) Sign-magnitude (b) 1's complement (c) 2's complement (d) Both (a) and (b)
Ans: (c) [Ch2 | NET]

Q5. Represent −9 in 8-bit 2's complement.
Ans: +9=00001001; flip=11110110; +1=11110111 [Ch2 | NET numerical]

Q6. Overflow in 2's complement addition occurs when: (a) Adding a positive and negative number (b) Adding two same-signed numbers gives an opposite-signed result (c) Never, overflow is impossible (d) Only when both operands are zero
Ans: (b) [Ch2 | NET]

Q7. What is the exponent bias in IEEE 754 single precision?
Ans: 127 [Ch2 | NET]

Q8. How many mantissa bits does IEEE 754 double precision use?
Ans: 52 [Ch2 | NET]

Q9. After R2 ← R1 in RTL, what happens to R1?
Ans: Unchanged (it's a copy) [Ch3 | NET]

Q10. Which shift type preserves the sign bit for negative numbers? (a) Logical shift (b) Arithmetic shift (c) Circular shift (d) None
Ans: (b) [Ch3 | NET]

Q11. Which addressing mode requires an EXTRA memory access? (a) Immediate (b) Register (c) Indirect (d) Direct
Ans: (c) [Ch4 | NET]

Q12. What must the CPU save first when handling an interrupt?
Ans: The return address (PC) [Ch4 | NET]

Q13. What problem does a two-pass assembler specifically solve?
Ans: Forward references [Ch5 | NET]

Q14. Why is a Stack used for subroutine return addresses rather than a fixed location?
Ans: Its LIFO order naturally supports nested/recursive calls [Ch5 | NET]

Q15. Which instruction format uses an implied accumulator? (a) Three-address (b) Two-address (c) One-address (d) Zero-address
Ans: (c) [Ch6 | NET]

Q16. Which architecture restricts memory access to ONLY Load/Store instructions? (a) CISC (b) RISC (c) Both (d) Neither
Ans: (b) [Ch6 | NET]

Q17. Evaluate postfix: 3 4 + 5 * using a stack.
Ans: Push3,4→[3,4]. '+'→7→[7]. Push5→[7,5]. '*'→35. Result=35 [Ch6 | JRF numerical]

Q18. Does pipelining reduce individual instruction latency? (a) Yes (b) No, it improves throughput (c) Only for RISC (d) Only with forwarding
Ans: (b) [Ch7 | NET]

Q19. A 5-stage pipeline executes 60 instructions. Find the pipelined execution time.
Ans: k+(n−1)=5+59=64 cycles [Ch7 | NET numerical]

Q20. Which hazard is a "genuine" data hazard (not fixable by renaming)? (a) WAR (b) WAW (c) RAW (d) Structural
Ans: (c) [Ch7 | JRF]

Q21. What causes a Control Hazard?
Ans: A branch instruction whose outcome/target is not yet known [Ch7 | NET]

Q22. Cache access=6ns, memory=90ns, hit ratio=0.9. Find AAT.
Ans: 0.9×6+0.1×90=5.4+9=14.4ns [Ch8 | NET numerical]

Q23. Cache has 32 lines. Using direct mapping, which line does block 100 map to?
Ans: 100 mod 32 = 4 [Ch8 | NET numerical]

Q24. Which cache mapping allows a block to go into ANY line? (a) Direct (b) Fully associative (c) Set-associative only (d) None
Ans: (b) [Ch8 | NET]

Q25. Which write policy updates main memory only when the cache line is evicted? (a) Write-through (b) Write-back (c) Both equally (d) Neither
Ans: (b) [Ch8 | NET]

Q26. What indicates a cache line has been modified and needs writing back?
Ans: The dirty bit [Ch8 | NET]

Q27. A basic Encoder assumes: (a) Multiple inputs active simultaneously (b) Only one input active at a time (c) No inputs active (d) All inputs always active
Ans: (b) [Ch1 | NET]

Q28. Which representation is used in virtually all modern computer hardware for signed integers?
Ans: 2's complement [Ch2 | NET]

Q29. Compute 6+(−2) using 8-bit 2's complement (show the result in decimal).
Ans: 6=00000110; −2=11111110; sum=100000100→discard carry→00000100=4 [Ch2 | JRF numerical]

Q30. Which microoperation type includes AND, OR, XOR?
Ans: Logic microoperations [Ch3 | NET]

Q31. What does the "mode bit" in an instruction typically indicate?
Ans: Whether addressing is direct or indirect [Ch4 | NET]

Q32. What happens after an ISR completes execution?
Ans: The saved PC is restored, resuming the interrupted program [Ch4 | NET]

Q33. A one-pass assembler struggles most with: (a) Backward references (b) Forward references (c) Comments (d) Blank lines
Ans: (b) [Ch5 | NET]

Q34. Which instruction format is naturally suited to postfix (Reverse Polish) expression evaluation? (a) Three-address (b) Two-address (c) One-address (d) Zero-address (stack)
Ans: (d) [Ch6 | NET]

Q35. RISC compilers are generally: (a) Simpler than CISC compilers (b) More complex than CISC compilers (c) Identical in complexity (d) Not needed at all
Ans: (b) [Ch6 | JRF]

Q36. A 3-stage pipeline processes 30 instructions. Find the speedup over non-pipelined execution.
Ans: Non-pipelined=3×30=90; Pipelined=3+29=32; Speedup=90/32≈2.81 [Ch7 | JRF numerical]

Q37. Forwarding (bypassing) cannot solve which specific data hazard case?
Ans: Load-use hazard (value not yet computed/available) [Ch7 | JRF]

Q38. What two types of locality does memory hierarchy/caching rely on?
Ans: Temporal locality and Spatial locality [Ch8 | NET]

Q39. Which replacement policy evicts the oldest-loaded line regardless of recent use? (a) LRU (b) FIFO (c) Random (d) None
Ans: (b) [Ch8 | NET]

Q40. Which cache mapping is a middle ground between direct and fully associative?
Ans: Set-associative mapping [Ch8 | NET]

Q41. A Full Adder differs from a Half Adder by having: (a) An extra output (b) A carry-in input (c) Fewer inputs (d) No sum output
Ans: (b) [Ch1 | NET]

Q42. Which addressing mode has NO memory access needed to fetch the operand (it's in the instruction itself)?
Ans: Immediate addressing [Ch4 | NET]

Q43. Gray Code is primarily useful because: (a) It's shorter than binary (b) Only one bit changes between consecutive values (c) It supports negative numbers (d) It's faster to add
Ans: (b) [Ch2 | NET]

Q44. Which hazard type arises from two instructions needing the same hardware resource?
Ans: Structural hazard [Ch7 | NET]

Q45. Which of these is FALSE? (a) Write-through always keeps cache and memory consistent (b) Write-back can leave memory temporarily stale (needs a dirty bit) (c) Write-back is generally faster for repeated writes (d) Write-through never accesses main memory
Ans: (d) — write-through DOES access main memory on every write; that's its defining trait. [Ch8 | JRF]

— End of Mock Test — Cross-check your score, revisit the "Don't Confuse" and "JRF Challenge Zone" boxes for any topic you missed, then re-attempt after 48 hours. —

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